1. Field of the Invention
This invention relates to the field of physical circuit design and, more particularly to the placement of a design.
2. Description of the Related Art
Designs for both application specific integrated circuits (ASIC's) and field programmable gate arrays (FPGA's) have become increasingly complex and heterogeneous. Modern ASIC and FPGA designs can include a variety of different components or resources including, but not limited to, block random access memory (RAM), multipliers, processors, and the like. Further, modern circuit designs incorporate different wiring materials for routing signals of differing lengths in any of a variety of directions. Typically, each material has unique properties which cause signal propagation delays to vary with the type of wiring material used. This increasing complexity makes placement of circuit design components more cumbersome.
As a result, timing driven placement has become increasingly important in very large scale integration (VLSI) design. Placement refers to the assignment of a component to a particular physical location in an ASIC or FPGA design. The objective of a placer is to assign locations to components such that signals can be routed using minimal resources and/or with minimal delay as governed by circuit design constraints. Typically, the placement function is based upon wire length and timing as determined using estimates of the time required for a signal to propagate the length of a connection. Such delay estimates, however, can be less than accurate as the estimates are not based upon actual routing data for the circuit design.
One reason for the potential inaccuracy of delay estimates is the variety of different wiring resources available within a circuit design. As noted, a variety of different wiring materials can be used, each having a different set of physical properties and corresponding signal propagation delay characteristics. Accordingly, the signal propagation delay between two pins may not be directly proportional to the distance between the pins. For instance, a signal may require more time to travel a connection spanning a distance of 4 units than a connection spanning a distance of 6 units. Such is the case, for example, where more than one type of wiring material is needed to route a particular signal or connection.
In consequence, many placement errors are not found until the placement phase has completed and the detailed routing phase of circuit design begins. Still, conventional placing tools continue to rely upon timing estimates and have no knowledge of how signal routing is to be accomplished for the circuit design.
What is needed is a technique where routing functions can be incorporated within the placement phase such that the resulting design placement quality is improved.